1. Field of the Invention
The present invention relates to the manufacturing of semiconductor components from a single-crystal silicon wafer.
2. Discussion of the Related Art
To manufacture discrete or integrated silicon semiconductor components, wafers are first cut in a single-crystal silicon ingot, in which many identical components are generally formed. The wafers are generally polished to obtain a surface evenness and a parallelism adapted to the subsequent wafer processings.
The polished wafers are then submitted to different doping processes to create semiconductive regions having different doping levels according to the patterns of the components to be made. According to the applications, generally, in the case of integrated circuits, the components are formed from a so-called xe2x80x9cfrontxe2x80x9d surface of the wafer and all corresponding metal contacts are on the front surface. For power or high voltage components, the components are formed in the thickness of the silicon wafer from the front and rear surfaces and the wafers then further include one or several contacts on their rear surface.
The different steps (masking, insulator deposition or growth, implantation/diffusion, cleaning, etc.) of manufacturing of semiconductor components require multiple handling of the silicon wafers by batches or individually. However, silicon wafers are very fragile (brittle) and this handling generates very high risks of breakage. Further, the larger the surface, the more fragile the wafer for a given thickness.
To solve this problem of fragility, the wafers are given a minimum thickness which depends on their diameter. The present dimensions of silicon wafers range between 100 mm and 200 mm of diameter and still greater diameters are envisaged. For example, for wafers of 200 mm of diameter in which integrated circuits are to be formed, a thickness on the order of 800 xcexcm is generally provided.
Most often, the silicon wafer has to be thinned (rectified) by its rear surface before cutting up the integrated circuits and mounting them in packages. Such a rectification can have several aims.
A first aim is to respect the dimensions of packages designed to receive circuits formed in transistors of lower diameter (and thus, of a lower thickness).
A second aim is to reduce or eliminate parasitic implantations/diffusions present at the rear surface and likely to generate operating defects.
Such a rectification at the end of the wafer processing method reduces breakage risks during the first steps of processing of the entire wafers. However, the thinned wafers become extremely fragile for the subsequent steps (metallization, cleaning, chip cutting-up, etc.) and handling that they require. Further, this mechanical fragility is reflected in the implemented integrated circuit chips.
A currently used method to thin the wafers at the end of the integrated circuit manufacturing process includes using a diamond grinding wheel to rectify the rear surface of the wafers and thus decrease their final thickness.
To implement power components, the silicon wafer is doped from both its surfaces. The final thickness of the wafer thus has to be set before the steps of manufacturing of the components. The silicon wafer thus is, in an initial rectification, brought down to the final substrate thickness (generally between 200 xcexcm and 400 xcexcm according to the wafer diameter). In this technology, a mechano-chemical polishing method which obtains a better surface evenness than grinding or chemical etch methods (which are other rectification methods) is generally used.
It would be desirable to be able to further decrease the wafer thickness, in particular, to facilitate the implantation/diffusion operations in the wafer thickness. However, such a decrease in thickness is not presently envisaged for reasons of fragility. Indeed, the wafer thickness limit is presently set by the minimum acceptable mechanical resistance criterion not to have too many losses due to handling. With the present thicknesses included between 200 xcexcm and 400 xcexcm, the wafers are already extremely brittle with respect to wafers used to form integrated circuits.
An object of the present invention is to provide a novel silicon wafer which is less fragile than present wafers and which, in particular, is less brittle.
Another object of the present invention is to provide such a silicon wafer having a substantially constant thickness.
Another object of the present invention is to provide a silicon wafer that improves the mechanical resistance of integrated circuits made from this wafer.
A characteristic of the present invention is to provide a thinning of a silicon wafer down to a thickness lower than approximately 80 xcexcm.
While the fragility of a wafer of low thickness in the state of the art results in increasing its thickness, the present invention provides, conversely, to decrease the wafer thickness. Indeed, the applicant has found that by passing under a thickness threshold on the order of 80 xcexcm, the silicon wafer is no longer brittle. It becomes flexible.
Referring to other materials, it could be thought that the fragility remains, for silicon, associated with the thickness. Indeed, silicon oxide (SiO2) which is currently used in extremely low thicknesses (from a few hundred angstroms to a few xcexcm) remains very brittle. To make silicon oxide less brittle, it is necessary to incorporate additives therein to produce glasses which, at given thicknesses and according to the additives used, can become less brittle. However, such additions are not easily compatible with the use of silicon in the field of semiconductors.
Thus, with respect to the state of the art, the present invention has at least three surprising effects.
A first surprising effect is that a wafer of a thickness lower than 80 xcexcm bends rather than break when undergoing mechanical stress.
A second surprising effect is that the wafer recovers its initial planar shape as soon as the mechanical stress disappears and bears no mark of the performed deflection.
A third surprising effect is that the wafer flexibility is accompanied by no alteration of the single-crystal silicon forming it as concerns its function as a semiconductor material.
Further, these features are independent from the crystal plane in which the silicon ingot from which the wafer is obtained is formed.
Another object of the present invention is to provide a method of thinning of a silicon wafer which is particularly adapted to obtaining silicon wafers of very low and substantially constant thickness.
To achieve this object, a characteristic of the present invention is to provide a step of mechano-chemical polishing in which the holding of the wafer against its bearing is only performed by a molecular vacuum between the wafer and its bearing.
More specifically, the present invention provides a single-crystal silicon wafer having a thickness lower than 80 xcexcm.
According to an advantage of the present invention, the silicon wafer is flexible and deflection-resilient.
According to an embodiment of the present invention, the silicon wafer has a given thickness ranging between 25 and 60 xcexcm.
According to an embodiment of the present invention, the silicon wafer forms a substrate for manufacturing semiconductor power components.
According to an embodiment of the present invention, the silicon wafer comprises, on a front surface, elements defining an integrated circuit.
The present invention also provides a method of thinning of a single-crystal silicon comprising thinning the wafer until a thickness lower than 80 xcexcm is obtained.
According to an embodiment of the present invention, this method comprises performing a rectification by mechano-chemical polishing of at least one first surface of the silicon wafer and of hanging the wafer to a holding device meant to be driven in an epicycloidal rotating motion with respect to a polishing felt, only by creating a molecular vacuum between the second surface of the wafer and a planar bearing of the holding device.
According to an embodiment of the present invention, the method comprises performing a chemical etch of at least one first surface of the wafer, before performing the mechano-chemical polishing.
The present invention also provides a semiconductor power component comprising a silicon substrate of a thickness lower than 80 xcexcm.
The present invention also provides an integrated circuit chip of a thickness lower than 80 xcexcm.
The present invention also provides a silicon wafer having a thickness of less than about 80 microns and a thickness variation less than xc2x110 microns.
The present invention also provides a single-crystal wafer having a thickness of less than about 80 microns, and surfaces of the silicon wafer being free of overlying layers. Within this disclosure, the term xe2x80x9coverlying layerxe2x80x9d is meant to refer to any layer that is deposited or grown on the surface of the wafer for processing such as epitaxial silicon layers, silicon oxide layers, metal layers, and others.
The present invention also provides a silicon wafer having surfaces free of overlying layers and a thickness variation of less than xc2x110 microns, and the silicon wafer being substantially planar in an unstressed condition and bendable to a non-planar shape in response to a mechanical stress.
The present invention also provides a semiconductor device having a thickness of less than about 80 microns.
The present invention also provides a method for making a single crystal silicon wafer including the step of thinning the silicon wafer having surfaces free of overlying layers to a thickness of less than about 80 microns.
The present invention also provides a method of making a semiconductor device including the step of forming an overlying layer on a silicon substrate, when the silicon substrate has a thickness of less than about 80 microns.
The patent application DD-A-217 246 discloses a silicon wafer that can have a thickness lower than 50 xcexcm for X-rays analysis. This document teaches away from any manufacturing by polishing and indicates that the used manufacturing method leads to thickness variations of xc2x110 xcexcm. This means that a wafer having a nominal thickness of 50 xcexcm will in some places have a thickness of 40 xcexcm and at other places a thickness of 60 xcexcm. So, the wafer is inadequate for constituting a semiconductor component substrate.
By contrast, an advantage of the polishing method according to the invention is that it provides wafers having a substantially constant thickness.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments.